The invention relates to a circuit for addition of multiple binary numbers
There are numerous applications where binary numbers need to be added. A circuit for addition of three binary numbers each having four digits may include three 3-to-2-compressors for each of the four digits of the three binary numbers Each 3-to-2-compressor may include three operand inputs a, b, c for the k-th (0<k<3) digits of the three binary numbers and two outputs: a sum output sum and a carry output car. The sum output sum transmit the result of a XOR-operation on the three operand inputs (sum=a XOR b XOR c) and the carry output car transmits the result of an operation car=(a AND b) OR (a AND c) OR (b AND c). In case four binary numbers have to be added, two 3-to-2-compressors for each digit may be used. The first 3-to-2-compressor may receive a bit from the respective digit three of the numbers, and the second 3-to-2-compressor may receive the carry output from the first 3-to-2-compressor and a carry output of the first 3-to-2-compressor of a lower digit.
3-to-2-compressors may be implemented in pass transistor logic, wherein transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages. 3-to-2-compressors implemented in pass transistor logic may be fast but consume a large surface area.
Hence, there may be a need for a less surface area consuming circuit for addition of multiple binary numbers.